NXP Semiconductors /LPC5410x /SCT0 /CONFIG

SCT operation

0 (DUAL_COUNTER): Dual counter. The SCT operates as two 16-bit counters named L and H.

1 (UNIFIED_COUNTER): Unified counter. The SCT operates as a unified 32-bit counter.

SCT clock mode

0 (SYSTEM_CLOCK): System clock. The system clock clocks the SCT and prescalers.

1 (PRESCALED_SYSTEM_CLO): Prescaled system clock. The SCT clock is the system clock, but the prescalers are enabled to count only when sampling of the input selected by the CKSEL field finds the selected edge. The minimum pulse width on the clock input is 1 bus clock period. This mode is the high-performance sampled-clock mode.

2 (SCT_INPUT): SCT input. The input selected by CKSEL clocks the SCT and prescalers. The input is synchronized to the system clock and possibly inverted. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power sampled-clock mode.

3 (PRESCALED_SCT_INPUT): Prescaled SCT input. The SCT and prescalers are clocked by the input edge selected by the CKSEL field. In this mode, most of the SCT is clocked by the (selected polarity of the) input. The outputs are switched synchronously to the input clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock.

SCT clock select

0 (INPUT_0_RISING_EDGES): Input 0 rising edges.

1 (INPUT_0_FALLING_EDGE): Input 0 falling edges.

2 (INPUT_1_RISING_EDGES): Input 1 rising edges.

3 (INPUT_1_FALLING_EDGE): Input 1 falling edges.

4 (INPUT_2_RISING_EDGES): Input 2 rising edges.

5 (INPUT_2_FALLING_EDGE): Input 2 falling edges.

6 (INPUT_3_RISING_EDGES): Input 3 rising edges.

7 (INPUT_3_FALLING_EDGE): Input 3 falling edges.

8 (INPUT_4_RISING_EDGES): Input 4 rising edges.

9 (INPUT_4_FALLING_EDGE): Input 4 falling edges.

10 (INPUT_5_RISING_EDGES): Input 5 rising edges.

11 (INPUT_5_FALLING_EDGE): Input 5 falling edges.

12 (INPUT_6_RISING_EDGES): Input 6 rising edges.

13 (INPUT_6_FALLING_EDGE): Input 6 falling edges.

14 (INPUT_7_RISING_EDGES): Input 7 rising edges.

15 (INPUT_7_FALLING_EDGE): Input 7 falling edges.

A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.

A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.

Synchronization for input n (bit 9 = input 0, bit 10 = input 1,…, bit 14 = input 5). A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CLKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used.

Reserved. Read value is undefined, only zero should be written.

A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.

A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.

Reserved. Read value is undefined, only zero should be written.